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MC100LVEP34 2.5V / 3.3V ECL /2, /4, /8 Clock Generation Chip
The MC100LVEP34 is a low skew /2, /4, /8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple LVEP34s in a system. Single-ended CLK input operation is limited to a VCC 3.0 V in PECL mode, or VEE -3.0 V in NECL mode.
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MARKING DIAGRAMS*
16 16 1 SO-16 D SUFFIX CASE 751B 1 16 16 1 TSSOP-16 DT SUFFIX CASE 948F A L, WL Y W, WW 100 LVEP34 ALYW 1 100LVEP34 AWLYWW
* * * * *
35 ps Output-to-Output Skew Synchronous Enable/Disable Master Reset for Synchronization The 100 Series Contains Temperature Compensation. PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V with VEE = -2.375 V to -3.8 V Open Input Default State
= Assembly Location = Wafer Lot = Year = Work Week
*For additional information, refer to Application Note AND8002/D
* NECL Mode Operating Range: VCC = 0 V * * LVDS Input Compatible
ORDERING INFORMATION
Device MC100LVEP34D MC100LVEP34DR2 MC100LVEP34DT Package SO-16 SO-16 TSSOP-16 Shipping 48 Units/Rail 2500 Units/Reel 96 Units/Rail 2500 Units/Reel
MC100LVEP34DTR2 TSSOP-16
(c) Semiconductor Components Industries, LLC, 2001
1
September, 2001 - Rev. 3
Publication Order Number: MC100LVEP34/D
MC100LVEP34
PIN DESCRIPTION
PIN Q0 1 Q Q0 2 R VCC 3 Q D 14 NC /2 15 EN 16 VCC CLK*, CLK** EN* MR* Q0, Q0 Q1, Q1 Q2, Q2 VBB Q1 4 Q Q1 5 R VCC 6 11 VBB /4 12 CLK 13 CLK VCC VEE NC ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Diff /2 Outputs ECL Diff /4 Outputs ECL Diff /8 Outputs Reference Voltage Output Positive Supply Negative Supply No Connect FUNCTION
R
* Pins will default LOW when left open. ** Pins will default to VCC/2 when left open.
FUNCTION TABLE
Q2 7 Q /8 Q2 8 R 9 VEE 10 MR CLK Z ZZ X EN L H X MR L L H FUNCTION Divide Hold Q0-3 Reset Q0-3
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Z = Low-to-High Transition ZZ = High-to-Low Transition
Figure 1. 16-Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW 37.5 kW > 2 kV > 200 V > 2 kxV Level 1 UL 94 V-0 A @ 0.125 in 28 to 34 210 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
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MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout IBB TA Tstg JA JC JA JC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage C ode u o age NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Wave Solder 0 LFPM 500 LFPM std bd 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 16 SOIC 16 SOIC 16 SOIC 16 TSSOP 16 TSSOP 16 TSSOP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 100 60 33 to 36 138 108 33 to 36 265 Units V V V V mA mA mA C C C/W C/W C/W C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
100EP DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 3)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single Ended) (Note 5) Input LOW Voltage (Single Ended) (Note 5) Input HIGH Voltage Common Mode Range (Differential) (Note 5, Note 6) Input HIGH Current Input LOW Current D D 0.5 -150 Min 40 1355 555 1335 555 1.2 Typ 50 1480 680 Max 60 1605 925 1620 875 3.3 150 0.5 -150 Min 40 1355 555 1335 555 1.2 25C Typ 50 1480 680 Max 60 1605 925 1620 875 3.3 150 0.5 -150 Min 42 1355 555 1275 555 1.2 85C Typ 52 1480 680 Max 62 1605 925 1620 875 3.3 150 Unit mA mV mV mV mV V A A
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. 4. All loading with 50 ohms to VCC-2.0 volts. 5. Do not use VBB at VCC < 3.0 V. Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode. 6. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC100LVEP34
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 7)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Output Voltage Reference (Note 9) Input HIGH Voltage Common Mode Range (Differential) (Note 10) Input HIGH Current Input LOW Current D D 0.5 -150 Min 40 2155 1355 2075 1355 1775 1.2 1875 Typ 50 2280 1570 Max 60 2405 1725 2420 1675 1975 3.3 150 0.5 -150 Min 40 2155 1355 2075 1355 1775 1.2 1875 25C Typ 50 2280 1570 Max 60 2405 1725 2420 1675 1975 3.3 150 0.5 -150 Min 42 2155 1355 2075 1355 1775 1.2 1875 85C Typ 52 2280 1570 Max 62 2405 1725 2420 1675 1975 3.3 150 Unit mA mV mV mV mV mV V A A
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.5 V. 8. All loading with 50 ohms to VCC-2.0 volts. 9. Single ended input CLK pin operation is limited to VCC 3.0 V in PECL mode. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.8 V to -2.375 V (Note 11)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 12) Output LOW Voltage (Note 12) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Output Voltage Reference (Note 13) Input HIGH Voltage Common Mode Range (Differential) (Note 14) Input HIGH Current Input LOW Current D D 0.5 -150 Min 40 -1145 -1945 -1225 -1945 -1525 -1425 Typ 50 -1020 -1700 Max 60 -895 -1575 -880 -1625 -1325 0.0 150 0.5 -150 Min 40 -1145 -1945 -1225 -1945 -1525 -1425 25C Typ 50 -1020 -1700 Max 60 -895 -1575 -880 -1625 -1325 0.0 150 0.5 -150 Min 42 -1145 -1945 -1225 -1945 -1525 -1425 85C Typ 52 -1020 -1700 Max 62 -895 -1575 -880 -1625 -1325 0.0 150 Unit mA mV mV mV mV mV V A A
VEE+1.2
VEE+1.2
VEE+1.2
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 11. Input and output parameters vary 1:1 with VCC. 12. All loading with 50 ohms to VCC-2.0 volts. 13. Single ended input CLK pin operation is limited to VEE -3.0 V in NECL mode. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC100LVEP34
AC CHARACTERISTICS VCC= 0 V; VEE= -3.8 V to -2.375 V or VCC= 2.375 V to 3.8 V; VEE= 0 V (Note 15)
-40C Symbol fmax tPLH tPHL tJITTER tS tH tRR VPP tr tf Characteristic Maximum Toggle Frequency (See Figure 4. Fmax/JITTER) Propagation Delay to Output CLK to Q0, Q1, Q2 MR to Q Min 2.8 550 500 650 600 <1 150 200 300 150 90 170 50 100 200 1000 200 150 200 300 150 100 180 750 700 Typ Max Min 2.8 600 550 700 650 <1 50 100 200 1000 250 150 200 300 150 120 200 800 750 25C Typ Max Min 2.8 650 600 750 700 <1 50 100 200 1000 280 850 800 85C Typ Max Unit GHz ps ps ps ps ps mV ps
Cycle-to-Cycle Jitter (See Figure 4. Fmax/JITTER) Setup Time EN Hold Time EN Set/Reset Recovery Input Swing (Note 16) Output Rise/Fall Times Q (20% - 80%)
15. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V. 16. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of 40.
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MC100LVEP34
There are two distinct functional relationships between the Master Reset and Clock:
Internal Clock Disabled MR CLK Q0 Q1 Q2 EN Internal Clock Enabled
CASE 1: If the MR is de-asserted (L-H), while the Clock is still high, the outputs will follow the first ensuing clock rising edge.
Internal Clock Disabled MR CLK Q0 Q1 Q2 EN Internal Clock Enabled
CASE 2: If the MR is de-asserted (L-H), after the Clock has transitioned low, the outputs will follow the second ensuing clock rising edge. Figure 2. Timing Diagrams
The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted.
TRR CLOCK CLOCK
TRR
MR
MR
OUTPUT
OUTPUT
CASE 1 Figure 3. Reset Recovery Time
CASE 2
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MC100LVEP34
900 800 VOUTpp (mV) 700 600 500 400 300 200 100 0 0 1000 2000 3000 4000 5000 6000 FREQUENCY (MHz) JITTEROUT ps (RMS) 1 B2 B4 / 8 9 8 7 6 5 4 3 2
Figure 4. Fmax/Jitter
Q Driver Device Qb 50 W 50 W
D Receiver Device Db
V TT V TT = V CC - 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404 AN1405 AN1504 AN1568 AN1650 AND8002 AND8020
- - - - - - -
ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs Marking and Date Codes Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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MC100LVEP34
PACKAGE DIMENSIONS
SO-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC100LVEP34
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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CCC EE CCC EE
SECTION N-N
-W-
DIM A B C D F G H J J1 K K1 L M
MC100LVEP34
Notes
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Notes
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MC100LVEP34
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PUBLICATION ORDERING INFORMATION
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MC100LVEP34/D

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